1. Field of the Invention
The present invention relates to a semiconductor memory and a fabrication method for the semiconductor memory. In particular, it relates to gate structures of memory cells for the semiconductor memories in which miniaturization of cell size has advanced.
2. Description of the Related Art
In accordance with the advancement of semiconductor technology, especially with the development of microelectronic fabrication technology, miniaturization of memory cells and high integration of semiconductor memories have progressed. However, the miniaturization of memory cells causes problems of non-uniform distortion of the geometries and sizes of the respective memory cells due to processing unevenness, pattern misalignments caused during lithography processes, or the like. Therefore, there is a need to provide electrically erasable programmable read-only memory (EEPROM) capable of suppressing the increase of the dispersion in the respective capacitive coupling ratios among multiple memory cells. In a memory cell matrix in which miniaturization of the memory cells are supposed to be advanced, a specific memory cell implemented by a stacked gate architecture (hereinafter called “the stacked gate memory cell”), whose gate structure encompasses a gate insulator on a p-type silicon substrate, a floating gate electrode stacked on the gate insulator, an inter-electrode dielectric stacked on the floating gate electrode and a control gate electrode stacked on the inter-electrode dielectric, has been proposed in Japanese Patent Application laid-open No. H8-316348. In the proposed stacked gate memory cell, the shape of the gate insulator and that of the inter-electrode dielectric are defined by self-aligned methodology, the gate insulator facing to the inter-electrode dielectric, sandwiching the floating gate electrode between the gate insulator and the inter-electrode dielectric.
To fabricate the stacked gate memory cell disclosed in H8-316348, for example, by thermal oxidation, a 10 nm-thick silicon oxide film, which becomes a gate insulator (tunneling oxide film), is grown across the surface of the p-type silicon substrate. A first polycrystalline silicon film, which becomes a floating gate electrode, is deposited on the gate insulator. Afterwards, the first polycrystalline silicon film, the gate insulator, and the semiconductor substrate are successively etched by a reactive ion etching (RIE) method, using a single etching mask, so as to form device isolation grooves with vertical walls. Next, after deposition of a new silicon oxide film across the resulting surface, which becomes device isolation films, the new silicon oxide film is etched until it reaches the surface of the first polycrystalline silicon film using a chemical mechanical polishing (CMP) method, then the device isolation films are buried in the device isolation grooves so as to achieve a planarized surface. An inter-electrode dielectric made of a stacked ONO film, which is made up of three films: a lower silicon oxide film (SiO2 film), a silicon nitride film (Si3N4 film), and an upper silicon oxide film (SiO2 film), is then formed across the entire surface. A second polycrystalline silicon film, which becomes a control gate electrode, is then formed on the inter-electrode dielectric. The second polycrystalline silicon film, the inter-electrode dielectric, and the first polycrystalline silicon film are vertically etched to the silicon substrate in order using the RIE method or the like using a single etching mask, so as to form a control gate electrode, an inter-electrode dielectric, and a floating gate electrode. Finally, n-type impurity ions are implanted using the control gate electrode as an implantation mask, and forming n-type diffused regions by a self-aligned methodology. Consequently, the stacked gate memory cells of EEPROM are complete.
In this way, the stacked gate memory cell used for flash memory or the like is fabricated such that the gate insulator (tunneling oxide film), the floating gate electrode, the inter-electrode dielectric, and the control gate electrode are stacked on the silicon substrate (semiconductor substrate) in order. FIG. 1A is an energy band diagram showing energy levels of the semiconductor substrate 1, the gate insulator (tunneling oxide film) 2, the floating gate electrode 21, the inter-electrode dielectric 11, and the control gate electrode 24 at the program operation of the stacked gate memory cell. For the semiconductor substrate 1, the conduction band edge Ec and the valence band edge Ev are represented. For the gate insulator 2 and the inter-electrode dielectric 11, only the conduction band edge is represented. For the floating gate electrode 21 and the control gate electrode 24, a metallic band structure is assumed and Fermi level EF is represented in FIG. 1A. When a program gate voltage is applied between a silicon substrate 1 and the control gate electrode 24, an electric field established across the gate insulator (tunneling oxide film) 2 generates tunneling current flowing through the gate insulator 2. Consequently, a predetermined amount of charge is stored in the floating gate electrode 21 within a predetermined time, resulting in a “programmed” memory cell. At the time of the program operation, the electric field is also established in the inter-electrode dielectric 11 so the cell structure and the material of the insulator film must be designed so that the amount of tunneling leakage current flowing through the inter-electrode dielectric 11 is negligible.
FIG. 1B is a corresponding energy band diagram illustrating energy levels of the semiconductor substrate 1, the gate insulator (tunneling oxide film) 2, the floating gate electrode 21, the inter-electrode dielectric 11, and the control gate electrode 24 at the erase operation of the stacked gate memory cell. By applying an erase gate voltage, which is reverse of the program gate voltage, the charge stored in the floating gate electrode 21 is discharged to the substrate, resulting in an “erased” memory cell. The program and erase operations generally need application of high program and erase gate voltages of 20 volts or greater so that a sufficient amount of tunneling current can flow through the gate insulator (tunneling insulator film) 2 made of a silicon oxide film or the like. This high voltage operation prevents stacked gate memory cells from being highly integrated, and power dissipation from decreasing.
In 1997 Symposium on VLSI Technology, Digest of Technical Papers p. 117, usage of an alumina (Al2O3) film as the material for the inter-electrode dielectric 11 has been proposed. Since the alumina film has a higher dielectric constant than the stacked ONO film, the capacitance area of the inter-electrode dielectric 11 can be reduced. Therefore, the alumina film is suitable for the miniaturization of cell size. Due to the same reason, a high dielectric oxide film such as a hafnium (Hf) oxide film, a zirconium (Zr) oxide film, or tantalum (Ta) oxide film, or an insulator film, which is obtained by doping an impurity into a high dielectric oxide film, may be used as the material of the inter-electrode dielectric 11.
However, if the above-mentioned high dielectric oxide film is formed on the floating gate electrode 21 made of silicon, a low dielectric silicon oxide film is formed on the interface between the inter-electrode dielectric 11 and the floating gate electrode 21. The interface low dielectric oxide film is formed during process stages such as cleaning the surface of the floating gate electrode 21, forming a high dielectric insulator film by, for example, CVD method, annealing to improve the film quality after formation of the high dielectric insulator film, and other related processes. In view of this problem, the surface of the floating gate electrode 21 may be nitrided, so as to prevent the formation of the silicon oxide film. Or, by the same reason, the silicon oxide film may be nitrided, so as to increase the dielectric constant of the interface low dielectric oxide film. Although either approach is not proved until actual results come out, it results in formation of an interface insulator 22 with a high barrier height and a lower dielectric constant than that of the inter-electrode dielectric 23, at the interface between the high dielectric inter-electrode dielectric 23 and the floating gate electrode 21.
FIG. 2A is an energy band diagram illustrating energy levels of the semiconductor substrate 1, the gate insulator (tunneling oxide film) 2, the floating gate electrode 21, the interface insulator 22, the inter-electrode dielectric 23, and the control gate electrode 24 at the program operation in this case. For the semiconductor substrate 1, the conduction band edge Ec and the valence band edge Ev are represented. For the gate insulator 2, the interface insulator 22, and the inter-electrode dielectric 23, only the conduction band edge is represented. For the floating gate electrode 21 and the control gate electrode 24, a metallic band structure is assumed and Fermi level EF is represented in FIG. 2A. When a program gate voltage is applied between the silicon substrate 1 and the control gate electrode 24, a predetermined amount of tunneling current flows through the gate insulator (tunneling oxide film) 2, and the charges are accumulated in the floating gate electrode 21. At this time, since a large voltage difference is established in the low dielectric constant interface insulator 22, effective tunneling distance for the mobile charges (carriers) within the floating gate electrode 21 becomes short, as is apparent through the comparison of FIGS. 1A and 2A. As a result, tunneling current flowing from the floating gate electrode 21 to the control gate electrode 24 increases, which makes storage of a predetermined amount of charge in the floating gate electrode 21 within a predetermined time impossible.
Note that FIG. 2B shows an energy band diagram at the erase operation. Applying the erase gate voltage, which is a reverse of the program gate voltage, discharges the stored charge. At this time, since the leakage current flowing through the inter-electrode dielectric 23 does not increase, the erase operation is successful.
As described above, since high program and erase gate voltages are needed for the earlier stacked gate memory cells, achievement of highly integrated stacked gate memory cells with reduced power dissipation is difficult. In addition, since tunneling current flowing from the floating gate electrode 21 to the control gate electrode 24 increases due to the presence of a low dielectric interface insulator 22, the programming speed decreases, or a stable and high performance program operation cannot be carried out.